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400Gb/s QSFP-DD SR8 100m Transceiver

LA-OT-400G-SR8
This product is a parallel 400Gb/s Quad Small Form Factor Pluggable--double density (QSFP-DD) optical module. It provides increased port density and total system cost savings.
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This product is a parallel 400Gb/s Quad Small Form Factor Pluggable--double density (QSFP-DD) optical module. It provides increased port density and total system cost savings. The QSFP-DD full- duplex optical module offers 8 independent transmit and receive channels, each capable of 53.125Gb/s operation for an aggregate data rate of 400Gb/s on 100 meters of OM3 multi-mode fiber. An optical fiber cable with an MTP/MPO-16 connector can be plugged into the QSFP-DD SR8 module receptacle. Proper alignment is ensured by the guide pins inside the receptacle. The cable usually cannot be twisted for proper channel to channel alignment. Electrical connection is achieved through an QSFP-DD MSA-compliant edge type connector. The central wavelengths of all the 8 parallel lanes are 850nm. It contains an optical MPO-16 connector for the optical interface and a 60-pin connector for the electrical interface. Host FEC is required to support up to 70m OM3 multi-mode fiber transmission. The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP-DD Multi-Source Agreement (MSA) Type 2. It has been designed to meet harshest external operating conditions including temperature, humidity and EMI interference.

Features
● QSFP-DD MSA compliant
● 8 parallel lanes on 850nm center wavelength
● Compliant to IEEE 802.3bs Specification
● Up to 100m transmission on multi-mode fiber (MMF) OM3 with FEC
● Operating case temperature: 0 to 70oC
● 8x53.125Gb/s electrical interface (400GAUI-8)
● Data Rate 53.125Gbps (PAM4) per channel.
● Maximum power consumption 12W
● MPO-16 connector
● RoHS compliant

Transceiver Block Diagram

Transceiver Block Diagram of 400Gb/s QSFP-DD SR8 100m Transceiver


Figure 1. Transceiver Block Diagram


Optical interface and Pin Assignment

The electrical pinout of the QSFP-DD module is shown as Figure 2. And Figure 3 shows the optical interface of MPO-16.

Optical interface and Pin Assignment of 400Gb/s QSFP-DD SR8 100m Transceiver


Figure 2. MSA Compliant Connector

Optical interface and Pin Assignment of 400Gb/s QSFP-DD SR8 100m Transceiver


Figure 3. MPO-16 Optical Connector Interface


Pin Definition

Pin

Logic

Symbol

Deion

Plug Sequence

1


GND

Ground

1B

2

CML-I

Tx2n

Transmitter Inverted Data Input

3B

3

CML-I

Tx2p

Transmitter Non-Inverted Data Input

3B

4


GND

Ground

1B

5

CML-I

Tx4n

Transmitter Inverted Data Input

3B

6

CML-I

Tx4p

Transmitter Non-Inverted Data Input

3B

7


GND

Ground

1B

8

LVTTL-I

ModSelL

Module Select

3B

9

LVTTL-I

ResetL

Module Reset

3B

10


VccRx

+3.3V Power Supply Receiver

2B

11

LVCMOS-

I/O

SCL

2-wire serial interface clock

3B

12

LVCMOS-

I/O

SDA

2-wire serial interface data

3B

13


GND

Ground

1B

14

CML-O

Rx3p

Receiver Non-Inverted Data Output

3B

15

CML-O

Rx3n

Receiver Inverted Data Output

3B

16

GND

Ground

1B


17

CML-O

Rx1p

Receiver Non-Inverted Data Output

3B

18

CML-O

Rx1n

Receiver Inverted Data Output

3B

19


GND

Ground

1B

20


GND

Ground

1B

21

CML-O

Rx2n

Receiver Inverted Data Output

3B

22

CML-O

Rx2p

Receiver Non-Inverted Data Output

3B

23


GND

Ground

1B

24

CML-O

Rx4n

Receiver Inverted Data Output

3B

25

CML-O

Rx4p

Receiver Non-Inverted Data Output

3B

26


GND

Ground

1B

27

LVTTL-O

ModPrsL

Module Present

3B

28

LVTTL-O

IntL

Interrupt

3B

29


VccTx

+3.3V Power supply transmitter

2B

30


Vcc1

+3.3V Power supply

2B

31

LVTTL-I

InitMode

Initialization mode; In legacy QSFP applications, the InitMode

pad is called LPMODE

3B

32


GND

Ground

1B

33

CML-I

Tx3p

Transmitter Non-Inverted Data Input

3B

34

CML-I

Tx3n

Transmitter Inverted Data Input

3B

35


GND

Ground

1B

36

CML-I

Tx1p

Transmitter Non-Inverted Data Input

3B

37

CML-I

Tx1n

Transmitter Inverted Data Input

3B

38


GND

Ground

1B

39


GND

Ground

1A

40

CML-I

Tx6n

Transmitter Inverted Data Input

3A

41

CML-I

Tx6p

Transmitter Non-Inverted Data Input

3A

42


GND

Ground

1A

43

CML-I

Tx8n

Transmitter Inverted Data Input

3A

44

CML-I

Tx8p

Transmitter Non-Inverted Data Input

3A

45


GND

Ground

1A

46


Reserved

For future use

3A

47


VS1

Module Vendor Specific 1

3A

48


VccRx1

3.3V Power Supply

2A

49


VS2

Module Vendor Specific 2

3A

50


VS3

Module Vendor Specific 3

3A

51


GND

Ground

1A

52

CML-O

Rx7p

Receiver Non-Inverted Data Output

3A

53

CML-O

Rx7n

Receiver Inverted Data Output

3A

54


GND

Ground

1A

55

CML-O

Rx5p

Receiver Non-Inverted Data Output

3A

56

CML-O

Rx5n

Receiver Inverted Data Output

3A

57


GND

Ground

1A

58


GND

Ground

1A

59

CML-O

Rx6n

Receiver Inverted Data Output

3A

60

CML-O

Rx6p

Receiver Non-Inverted Data Output

3A

61


GND

Ground

1A

62

CML-O

Rx8n

Receiver Inverted Data Output

3A

63

CML-O

Rx8p

Receiver Non-Inverted Data Output

3A

64


GND

Ground

1A

65


NC

No Connect

3A

66


Reserved

For future use

3A

67


VccTx1

3.3V Power Supply

2A

68


Vcc2

3.3V Power Supply

2A

69


Reserved

For Future Use

3A

70


GND

Ground

1A

71

CML-I

Tx7p

Transmitter Non-Inverted Data Input

3A

72

CML-I

Tx7n

Transmitter Inverted Data Input

3A

73


GND

Ground

1A

74

CML-I

Tx5p

Transmitter Non-Inverted Data Input

3A

75

CML-I

Tx5n

Transmitter Inverted Data Input

3A

76


GND

Ground

1A


Recommended Power Supply Filter

Recommended Power Supply Filter of 400Gb/s QSFP-DD SR8 100m Transceiver

Figure 4. Recommended Power Supply Filter


Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.


ParameterSymbolMinMaxUnitsNotes
Storage TemperatureTS-4085degC
Operating Case TemperatureTOP070degC
Power Supply VoltageVCC-0.53.6V

Relative Humidity

(non-condensation)

RH085%


Recommended Operating Conditions and Power Supply Requirements

ParameterSymbolMinTypicalMaxUnitsNotes
Operating Case TemperatureTOP0
70degC
Power Supply VoltageVCC3.1353.33.465V
Data Rate, each Lane

26.5625
GBdPAM4
Data Rate Accuracy
-100
100ppm
Pre-FEC Bit Error Ratio


2.4x10-4

Post-FEC Bit Error Ratio


1x10-12
1
Link Distance with OM3D0.5
100m2


Notes:

1. FEC provided by host system.

2. FEC required on host system to support maximum distance.


Electrical Characteristics

The following electrical acteristics are defined over the Recommended Operating Environment unless otherwise specified.


ParameterTestMinTypicalMaxUnitsNotes
Point
Power Consumption


12W
Supply CurrentIcc

3.63A
Transmitter (each Lane)
Signaling Rate, each LaneTP126.5625 ± 100 ppmGBd

Differential pk-pk 

Input Voltage Tolerance

TP1a900

mVpp1

Differential Termination 

Mismatch

TP1

10%


IEEE 802.3-



Differential Input 

Return Loss

TP12015dB


Equation


-8.30E-04


IEEE 802.3-



Differential to Common 

Mode Input Return Loss

TP12015dB


Equation


-8.30E-05
Module Stressed Input TestTP1aSee IEEE 802.3bs 120E.3.4.1
2

Single-ended Voltage 

Tolerance Range (Min)

TP1a-0.4 to 3.3V

DC Common Mode

 Input Voltage

TP1-350
2850mV3
Receiver (each Lane)

Signaling 

Rate, 

each lane

TP426.5625 ± 100 ppmGBd

Differential 

Peak-to-Peak 

Output Voltage

TP4

900mVpp

AC Common 

Mode Output 

Voltage, RMS

TP4

17.5mV

Differential 

Termination 

Mismatch

TP4

10%


IEEE 802.3-



Differential 

Output 

Return 

Loss

TP42015


Equation


-8.30E-01


IEEE 802.3-



Common to 

Differential 

Mode 

Conversion 

Return Loss

TP42015


Equation


-8.30E-02

Transition 

Time, 

20%

to 

80%

TP49.5

ps

Near-end 

Eye 

Symmetry

 Mask

TP4
0.265
UI
Width (ESMW)

Near-end 

Eye Height,

TP470

mV
Differential

Far-end 

Eye 

Symmetry 

Mask

TP4
0.2
UI
Width (ESMW)

Far-end 

Eye 

Height,

Differential

TP430

mV

Far-end 

Pre-cursor 

ISI Ratio

TP4-4.5
2.5%

Common 

Mode 

Output 

Voltage (Vcm)

TP4-350
2850mV3


Notes:

1. With the exception to IEEE 802.3bs 120E.3.1.2 that the pattern is PRBS31Q or scrambled idle.

2. Meets BER specified in IEEE 802.3bs 120E.1.1.

3. DC common mode voltage generated by the host. Specification includes effects of ground offset voltage.


Optical Characteristics

ParameterSymbolMinTypicalMaxUnitsNotes
Transmitter
Center WavelengthλC840850860nm
Data Rate, each Lane
26.5625 ± 100 ppmGBd
Modulation Format
PAM4

RMS Spectral Width∆λrms

0.6nmModulated

Average Launch 

Power, each  Lane

PAVG-6.5
4dBm1
Outer Optical Modulation





Amplitude (OMAouter), 

each  Lane

POMA-4.53dBm2

Launch Power in 

OMAouter minus

TDECQ, each Lane


-5.9

dB

Transmitter and  

Dispersion Eye

Clouser for PAM4, each Lane







TDECQ4.5dB
Extinction RatioER3

dB
Optical Return LossTOL

12dB
Tolerance

Average Launch Power of

OFF Transmitter, each Lane

Poff

-30dBm
Encircled Flux
≥ 86% at 19 μm

≤ 30% at 4.5 μm
Receiver
Center WavelengthλC840850860nm
Data Rate, each Lane
26.5625 ± 100 ppmGBd
Modulation Format
PAM4

Damage Threshold, each LaneTHd5

dBm3
Average Receive Power, each
-7.9
4dBm4
Lane

Receive Power 

(OMAouter), each Lane




3dBm
Receiver SensitivitySEN

-6.5dBm5
(OMAouter), each Lane
Stressed Receiver SensitivitySRS

-3dBm6
(OMAouter), each Lane
Receiver ReflectanceRR

-12dB
LOS AssertLOSA-30

dBm
LOS De-assertLOSD

-12dBm
LOS HysteresisLOSH0.5

dB

Stressed Conditions for Stress

Receiver Sensitivity (Note 7)

Stressed Eye Closure for

PAM4 (SECQ), Lane under Test



4
dB
OMAouter of each Aggressor Lane

3
dBm


Notes:

1. Average launch power, each lane (min) is informative and not the principal indicator of signal strength.
A transmitter with launch power below this value cannot be compliant; however,
a value above this does not ensure compliance.

2. Even if the TDECQ < 1 dB, the OMAouter (min) must exceed the minimum value specified here.

3. The receiver shall be able to tolerate, without damage, continuous exposure to an optical input signal having this average power level.

4. Average receive power, each lane (min) is informative and not the principal indicator of signal strength. A received power below this value cannot be compliant;
however, a value above this does not ensure compliance.

5. Receiver Sensitivity OMAouter, each lane (max) is informative and is defined for a BER of 2.4x10-4.

6. Measured with conformance test signal at receiver input for the BER of 2.4x10-4.

7. These test conditions are for measuring stressed receiver sensitivity. They are not acteristics of the receiver.


Digital Diagnostic Functions

The following digital diagnostic acteristics are defined over the normal operating conditions unless otherwise specified.


ParameterSymbolMinMaxUnitsNotes

Temperature  monitors

absolute error





Over operating temperature range
DMI_Temp-33degC
Supply voltage monitorDMI _VCC-0.10.1VOver full operating
absolute errorrange

Channel RX   power monitor

absolute error






DMI_RX_Ch-22dB1
Channel Bias currentDMI_Ibias_Ch-10%10%mA
monitor
Channel TX powerDMI_TX_Ch-22dB1
monitor absolute error


Notes:

1. Due to measurement accuracy of different fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.


Outline Drawing (mm)

Outline Drawing of 400Gb/s QSFP-DD SR8 100m Transceiver


Applications

● Data Center Interconnect

● 400G Ethernet

● InfiniBand interconnects

● Enterprise networking

Date Version Description Download
2025-03-17 Datasheet_400G QSFP-DD SR8 850nm 100m_LA-OT-400G-SR8
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